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OpenSPARC T1 regression failing

mzaman2013Sep 11 2015 — edited Sep 11 2015

Hello,

I am trying to simply run the regression test provided by the OpenSPARC T1 v1.7 package. I am running on Solaris 10, SPARC machine. Used the following command:

# sims -sim_type=ncv -novera_build -novera_run -group=thread1_mini -vcs_build_args=/export/home/rtl_cosim/verif/env/playback_dump.v

it completes the midas "SETUP, PREPROCESSING, SECTION PARSING, ASSEMBLY, LINK, POSTPROCESSING, COPY and CLEANUP PHASE". After that sims.log below:

sims: locating diag default.dat

sims: Looking for diag under $DV_ROOT/verif/diag

sims: Found diag under /export/home/mxm084100/rtl_cosim/verif/diag/efuse/default.dat

sims: creating sas sockets

sims: basconfig -DSFSR_CMP -DMMU_REG_CMP -DNIAGARA -DMEM_DEBUG -DINTR_TEST -DMEM_TEST -DSP0 -DRTL  -DVSOCKET=0  -DCSOCKET=10576

/export/home/mxm084100/rtl_cosim/tools/local/bas-release/bas,3.9

sed  's/common.exe/diag.exe/' /export/home/mxm084100/rtl_cosim/tools/local/bas-release/bas,3.9/home/common/common.sas | sed 's/common.conf/diag.conf/' | bw_cpp -B -DSFSR_CMP -DMMU_REG_CMP -DNIAGARA -DMEM_DEBUG -DINTR_TEST -DMEM_TEST -DSP0 -DRTL -DVSOCKET=0 -DCSOCKET=10576 | grep -v '^#' > diag.sas

sims: starting bas

sims: bas 

sims: waiting for pli socket to be opened

sims: #!/bin/csh -f

setenv LD_LIBRARY_PATH :/export/home/mxm084100/rtl_cosim/tools/SunOS/sparc/lib:/proj/cad/cadence/ius-8.2.sun4v/tools/lib

echo run 400 ms | ncverilog +nclibdirname+/export/home/mxm084100/rtl_cosim/model/core1/core1_2015_09_10_3/INCA_libs -r worklib.core1:v +name+core1 +ncsimexe+/export/home/mxm084100/rtl_cosim/tools/SunOS/sparc/ncsim +ncelabexe+/export/home/mxm084100/rtl_cosim/tools/SunOS/sparc/ncelab -s +BW_BFM7 +BW_BFM6 +BW_BFM5 +BW_BF

M4 +BW_BFM3 +BW_BFM2 +BW_BFM1 +SYSTEM_DV_MATCH=2 +RANK_DIMM +STACK_DIMM +hypervisor=1 +vera_exit_on_error +cpu_num=0 +dowarningfinish +doerrorfinish +csocket=10576 +vcs+dumpvarsoff +use_sas_tasks +finish_mask=1 +TIMEOUT=5000 +wait_cycle_to_kill=10 +tg_seed=1634648536 +good_trap=0000082000:1000122000 +bad_trap=00000820

20:1000122020 +nolog +efuse_data_file=efuse.img +asm_diag_name=nop.s +efuse_image_name=default.dat +dv_root=/export/home/mxm084100/rtl_cosim

sims: LD_LIBRARY_PATH is :/export/home/mxm084100/rtl_cosim/tools/SunOS/sparc/lib:/proj/cad/cadence/ius-8.2.sun4v/tools/lib

sims: NCV_HOME is /proj/cad/cadence/ius-8.2.sun4v

sims: setenv VERA_LIBDIR /export/home/mxm084100/rtl_cosim/model/core1/core1_2015_09_10_3/vera

sims: LM_LICENSE_FILE : 1700@dmv:5280@dmv:1717@dmv

sims: sim_start Thursday, September 10, 2015 07:02:23 PM CDT

sims: Caught a SIGDIE. ncverilog exited with an error at /export/home/mxm084100/rtl_cosim/tools/src/sims/sims,1.262 line 3024.

Under each test case, I am seeing this issue in the sim.log:

# more sim.log

ncverilog: 08.20-s006: (c) Copyright 1995-2009 Cadence Design Systems, Inc.

ncsim: 08.20-s006: (c) Copyright 1995-2009 Cadence Design Systems, Inc.

Loading snapshot worklib.core1:v .................... Done

=== OpenSPARC T1 PLI Version 1.0 ===

Copyright (c) 2001-2006 Sun Microsystems, Inc. All rights reserved.

ncsim> source /proj/cad/cadence/ius-8.2.sun4v/tools/inca/files/ncsimrc

ncsim> ncsim: *F,INTERR: INTERNAL ERROR

Observed simulation time : 0 FS + 0

-----------------------------------------------------------------

The tool has encountered an unexpected condition and must exit.

Contact Cadence Design Systems customer support about this

problem and provide enough information to help us reproduce it,

including the logfile that contains this error message.

  TOOL: ncsim   08.20-s006

  HOSTNAME: eng64988

  OPERATING SYSTEM: SunOS 5.10 Generic_147147-26 sun4v

  MESSAGE: rts_seghandler - SIGSEGV unexpected violation pc=0x4d7ba08 addr=0xaa000000

        Always stmt (file: /export/home/mxm084100/rtl_cosim/design/sys/iop/ctu/rtl/ctu_clsp_clkgn_1div.v, line: 215 in worklib.ctu_clsp_clkgn_1div [module])

-----------------------------------------------------------------

And this is the verilog code where it complained:

214 //synopsys translate_off
215    always @ ( /*AUTOSENSE*/div_dec or se or `CTU_PATH.io_pwron_rst_l)
216    begin
217         // getting out of bypass mode directly going into freq change
218         #1;
219        // U216
220        if(  (`CTU_PATH.io_pwron_rst_l === 1'b1) &
221            (({div_dec[9],div_dec[10],div_dec[11]} !== 3'b000) &
222             ({div_dec[9],div_dec[10],div_dec[11]}  !== 3'b100) &
223             ({div_dec[9],div_dec[10],div_dec[11]}  !== 3'b010) &
224             ({div_dec[9],div_dec[10],div_dec[11]}  !== 3'b001))
225          )
226 `ifdef MODELSIM
227            $display ( "CTU_not_one_hot_error",
228                 "Select signals to data path mux U216 are not one hot: %h",
229                  {div_dec[9],div_dec[10],div_dec[11]} );
230     `else
231            $error ( "CTU_not_one_hot_error",
232                 "Select signals to data path mux U216 are not one hot: %h",
233                  {div_dec[9],div_dec[10],div_dec[11]} );
234     `endif

I have seen a thread similar: simulation error, but it is quite old, and I don't have access to NCVerilog 5.3 or SUNCompiler 5.0

Is there any workaround?

This regression would help me create the stimuli for gate level simulation.

One more question is, does anyone know what technology library file to use to estimate power of each core from the Gate level netlist (generated by the "rsyn" command?



Any help/comment is appreciated.

Thanks

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Added on Sep 11 2015
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