Integration

Hi everybody,

we have experiencing an strage issue after increasing our heap size and nursery in Production from

-Xms2816M -Xmx2816M -Xns550M to -Xms4096M -Xmx4096M -Xns1024M

We need to resize this because a new application is being promoted, and we have tested it in Pre-PRO

The thing is that after the new size and before deploying the new app,
all the 'Old Collection Reasons' are due to 'Artifical: Cleaning up Finished Threads' and the top of the HEAP (4GB) is never reached

A sample:
[gcpause][Wed Feb 27 22:29:26 2013][01719] [OC#621] [---] 1498,525 ms (611967,663000-611969,161000) OC
[gcpause][Wed Feb 27 22:29:26 2013][01719] [OC#621] [con] 0,004 ms (611967,663000-611967,663000) OC:PreGC
[gcpause][Wed Feb 27 22:29:26 2013][01719] [OC#621] [pau] 1453,742 ms (611967,663000-611969,116000) OC:Main
[gcpause][Wed Feb 27 22:29:26 2013][01719] [OC#621] [con] 43,411 ms (611969,118000-611969,161000) OC:PostGC
[memory ][Wed Feb 27 22:29:26 2013][01719] [OC#621] 611967,663-611969,161: OC 2982855KB->1227524KB (4194304KB), 1,499 s, sum of pauses 1453,742 ms, longest pause 1453,742 ms.


After examinig the correponding JFR we haven't any issue or hotspot in the code that could justify this behaviour, in fact the same that works right with 2,8 GB HEAP
Googling hasn't given us any answer and the Support mates are requiring us some more information, but they say this is normal (something that I don't agree at all)

Any suggestion will be welcome ... thanks in advance

We're running:
java version "1.5.0_26"
Java(TM) Platform, Standard Edition for Business (build 1.5.0_26-b03)
Oracle JRockit(R) (build R28.1.1-14-139783-1.5.0_26-20101206-0241-linux-x86_64, compiled mode)

and:
HT is: not supported by the CPU, not enabled by the OS, not enabled in JRockit.
CPU: Intel Core 2 SSE SSE2 SSE3 SSSE3 SSE4.1 Core Intel64
Vendor: GenuineIntel
Family: Core 2
Model: Core 2
Name: Intel(R) Xeon(R) CPU X7460 @ 2.66GHz
Sockets: 4
Cores: 24
HWThreads: 24
Supports: On-Chip FPU
Supports: Virtual Mode Extensions
Supports: Debugging Extensions
Supports: Page Size Extensions
Supports: Time Stamp Counter
Supports: Model Specific Registers
Supports: Physical Address Extension
Supports: Machine Check Exceptions
Supports: CMPXCHG8B Instruction
Supports: On-Chip APIC
Supports: Fast System Call
Supports: Memory Type Range Registers
Supports: Page Global Enable
Supports: Machine Check Architecture
Supports: Conditional Mov Instruction
Supports: Page Attribute Table
Supports: 36-bit Page Size Extension
Supports: the CLFLUSH Instruction
Supports: the Debug Trace Store feature
Supports: ACPI registers in MSR space
Supports: Intel Architecture MMX Technology
Supports: Fast Float Point Save and Restore
Supports: Streaming SIMD extensions
Supports: Streaming SIMD extensions 2
Supports: Self-Snoop
Supports: Hyper Threading
Supports: Thermal Monitor
Supports: Streaming SIMD Extensions 3
Supports: 64-bit DS Area
Supports: MONITOR/MWAIT instructions
Supports: Virtual Machine Extensions
Supports: Enhanced Intel SpeedStep technology
Supports: Thermal Monitor 2
Supports: Supplemental Streaming SIMD Extensions 3
Supports: CMPXCHG16B
Supports: xTPR Update Control
Supports: Perfmon and Debug Capability
Supports: Direct Cache Access
Supports: Streaming SIMD extensions 4.1
Supports: LAHF/SAHF instruction support
Supports: SYSCALL/SYSRET
Supports: Intel 64 Architecture
[memory ][Wed Feb 20 20:29:57 2013][01719] Running with 32 bit heap and compressed references supporting 32GB heap.
[memory ][Wed Feb 20 20:29:57 2013][01719] GC mode: Garbage collection optimized for throughput, strategy: Generational Parallel Mark & Sweep.